Display device and its driving method

ABSTRACT

A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines. It is, therefore, possible to suppress an increase in the number of connection lines and of the logic circuit sections involving a high definition of a display device and hence to manufacture a display device in a high yield.

DESCRIPTION

1. Technical Field

The present invention relates to a display device such as a liquidcrystal display device which includes a plurality of display pixelsarranged in a matrix array, and its driving method.

2. Background Art

A liquid crystal display device has been used in many fields, such as atelevision, computer display and electronic notebook, and particularattention has been paid to liquid crystal display devices having lightweight, small thickness and low power dissipation.

In a liquid crystal projector, for example, white color light from alight source is spectrally divided by a dichroic mirror, etc., intothree primary colors, red, green and blue. These light color-componentsare incident on three independent liquid crystal devices to display ared, a green and a blue image, and these display images are againoptically combined to project a resultant image on a transmission or areflection screen for color display.

A liquid crystal display device for a liquid crystal projector has tomeet the requirements that an incident optical system and projectionoptical system be made small without increasing their size. It is alsorequired that, because the display image on the liquid crystal displaydevice is projected in an enlarged form onto a screen, the displaydevice be made compact and the display pixels be made at a fine pitch.

Attempts have been made, in such a liquid crystal display device, toform a display panel constructed of a plurality of display pixels, aswell as a drive circuit section driving these display pixels, as oneunit over a substrate to eliminate cumbersome interconnection betweenthe display panel and the drive circuit section.

The drive circuit section of the above-mentioned display device iscomprised mainly of a shift register array where normally a plurality ofshift registers are connected in one array. This is disclosed, forexample, SID 93 DIGEST p383-p386 "A 1.9-in.1.5-MPixel DriverFully-Integrated Poly-Si TFT-LCD for HDTV Projection".

However, since the shift register array is a type that transfers asignal sequentially through these shift registers, if there are anydefects, such as shorting, in part of the shift register array, then allthe downstream shift registers fail.

In order to eliminate this drawback, for example, Jpn. Pat. Appln. KOKAIPublication No. 62-271569 discloses using, as a drive circuit section ofthe display device, a driver circuit comprised of one pair of decodersinstead of shift register for outputting sequential pulses on the basisof a binary count value for counting a clock pulse and its invertedreplica.

If the drive circuit section is comprised mainly of decoders, when thereis any break or shorting in part of the interconnection, an output isnot obtained at an area corresponding to any defect area, but it ispossible to secure adequate reliability by, for example, providing onepair of decoders as a redundant unit in the drive circuit.

In the arrangement disclosed in Jpn. Pat. Appln. KOKAI Publication No.62-271569, however, the decoder has a plurality of logic circuitsections each corresponding to one scanning line or one signal line and,hence, not only the number of connection lines for transmitting numeralsignals but also the number of logic circuit sections is increased asdefinition of the display device increases and, conversely, this causesa fall in a manufacturing yield. Further, since the respective logiccircuit sections are arranged to correspond to one scanning line or onesignal line each, no adequate measure can be taken against high-speedoperation requirements resulting from the high definition of the displaydevice.

A method is known by which, in the case where the number of effectivescanning lines of a video signal, for example, is less than the numberof horizontal pixel lines, the display panel's horizontal pixel linesremaining as ones not corresponding to the effective scanning lines ofthe video signal are scanned during a vertical blanking period, etc., todisplay a black blank display. In the above-mentioned arrangement, it isdifficult to scan all the remaining horizontal pixel lines in a verybrief period of time. It is, therefore, not possible to expect anypositive black display.

The object of the present invention is to provide a display device tosolve the above-mentioned technical task, according to which it ispossible to markedly reduce any operation error.

Another object of the present invention is to provide a display deviceand drive method which can obtain a better display image even when thenumber of horizontal pixel lines of the display panel and number ofeffective scanning lines, or the number of the display pixels in onehorizontal pixel line and number of video data of the video signal,differ.

DISCLOSURE OF INVENTION

A display device of the present invention comprises:

a display panel having a plurality of signal lines and plurality ofscanning lines arranged in a matrix, a plurality of switching elementselectrically connected to the signal lines and scanning lines, and pixelelectrodes connected to the switching elements;

a scanning circuit section for supplying scanning signals to thescanning lines; and

a scanning control circuit section for supplying an n-bit input numeralsignal (n: 2 or more positive integer) and an inverted replica of theinput numeral signal to the scanning circuit section, wherein

the scanning circuit section comprises

input connection line group having sets of input connection lines forreceiving bits of the input numeral signal and bits of the invertedreplica of the input numeral signal,

a plurality of logic circuit sections, less in number than the scanninglines, for responding to combinations of the input numeral signal andthe inverted replica of the input numeral signal, and

output distributing means for assigning an output from one logic circuitsection to at least two scanning lines.

Further, a display device of the present invention comprises:

a display panel having a plurality of signal lines and plurality ofscanning lines arranged in a matrix, switching elements electricallyconnected to the signal lines and scanning lines and pixel electrodesconnected to the switching elements;

a select control circuit section for generating an n-bit input numeralsignal (n: 2 or more positive integer) and an inverted replica of theinput numeral signal; and

a video signal supplying circuit section for selecting, in apredetermined timing, input video signals based on the input numeralsignal and the inverted replica of the input numeral signal from theselect control circuit section and supplying selected video signals tothe signal line as video data, wherein

the video signal supplying circuit section comprises

an input connection line group having sets of input connection lines forreceiving bits of the input numeral signal and bits of the invertedreplica of the input numeral signal,

a plurality of logic circuit sections, less in number than the scanninglines, for responding to combinations of the input numeral signal andthe inverted replica of the input numeral signal, and

output distributing means for assigning an output from one logic circuitsection to at least two signal lines.

A method of the present invention is provided for driving a displaydevice for forming a display image based on video data of a video signalon a display panel including an array of horizontal pixel lines eachformed of a plurality of display pixels, the method comprising the stepsof, when the number of effective scanning lines in one vertical scanningperiod of the video signal is less than the number of the correspondinghorizontal pixel lines, displaying non-display data on at least onehorizontal pixel line not corresponding to the effective scanning lineof the video signal in a first period containing one vertical scanningperiod, and displaying non-display data on the other horizontal pixellines not corresponding to the effective scanning line of the videosignal in a second period containing another vertical scanning perioddifferent from the one vertical scanning period.

Further, a method of the present invention is provided for driving adisplay device for forming a display image based on video data of avideo signal on a display panel including an array of horizontal pixellines each formed of a plurality of display pixels, the methodcomprising the steps of, when the number of the video data in onehorizontal scanning period of the video signal is less than the numberof the display pixels of the horizontal pixel line, displayingnon-display data on at least one display pixel not corresponding to thevideo data in a first period, and displaying non-display data on anotherdisplay pixel not corresponding to the video data in a second perioddifferent from the first period.

According to the display device of the present invention, since thescanning circuit section or video signal supplying circuit sectionincludes fewer logic circuit sections less in number than the scanninglines or signal lines to be selected on the basis of an input numeralsignal from the select control circuit, it is possible to, for the highdefinition of the display device, prevent an increase in the number ofconnection lines for transmitting the numeral signal and the number oflogic circuit sections and hence to manufacture a display device in abetter yield. Further, using fewer number of logic circuit sectionsmakes it possible to suppress the operation frequency of the numeralsignal to a low extent and to provide an allowance for elementdesigning.

According to the method for driving the display device of the presentinvention, even if the number of the horizontal pixel lines of thedisplay panel and effective scanning lines of the video signal differ orif the number of the display pixels in one horizontal pixel line andnumber of video data of the video signal, differ, non-display data isdisplayed in a first period on at least one horizontal pixel line notcorresponding to the effective scanning line of the video signal, in asecond period different from the first period, on another horizontalpixel line not corresponding to the effective scanning line of the videosignal, or non-display data is displayed, in a first period, on at leastone display pixel not corresponding to the video data and in a secondperiod different from the first period, on another display pixel notcorresponding to the video data. By doing so, non-display data can bedisplayed on the non-display areas.

The scanning circuit section or video signal supply circuit section inthe display device is comprised of logic circuit sections forselectively producing outputs on the basis of an input numeral signalfrom the select control circuit section. By doing so, theabove-mentioned drive method can be readily realized in a simplearrangement.

BRIEF DESCRIPTION IF THE DRAWINGS

FIG. 1 is a view schematically showing an arrangement of a liquidcrystal projector according to one embodiment of the present invention;

FIG. 2 is a view schematically showing an arrangement of a liquidcrystal device shown in FIG. 1;

FIG. 3 is a view schematically showing an arrangement of a scanning linedrive circuit shown in FIG. 2;

FIG. 4 is a view schematically showing an arrangement of a video signalline drive circuit shown in FIG. 2;

FIG. 5 is a view showing one drive waveform diagram of the scanning linedrive circuit shown in FIG. 2;

FIG. 6 is a view showing another drive waveform diagram of the scanningline drive circuit shown in FIG. 2;

FIG. 7 is a view showing another drive waveform of the scanning linedrive circuit shown in FIG. 2;

FIG. 8 is a view showing one drive waveform diagram of a video signalline drive circuit shown in FIG. 2;

FIG. 9 is a view showing one form of an image displayed by the liquidcrystal projector shown in FIG. 1; and

FIG. 10 shows a voltage-light transmittance characteristic illustratinga relationship between of the transmittance and a voltage between apixel electrode and a common electrode of the liquid crystal deviceshown in FIG. 1.

BEST MODE OF CARRYING OUT THE INVENTION

A liquid-crystal projector according to one embodiment of the presentinvention will be explained below with reference to the accompanyingdrawings.

FIG. 1 is a view schematically showing an arrangement of the liquidcrystal projector 1. The liquid crystal projector 1 comprises a lightsource 2, a reflection mirror 3 for reflecting a light source beamdirected toward a back surface of the light source 2, a first aperturemask 4 for narrowing down the light beam coming from a light source 2, alight source optical lens 5 for allowing the light source beam whichpasses through the aperture mask 4 to appear as parallel beams, a firstdichroic mirror 7 for allowing a red-color component R in the light beamwhich passes through the light source optical lens 5 to be reflected andgreen and blue color components G and B to be transmitted, a firstreflection mirror 11 for allowing the red color component R which isreflected by the first dichroic mirror 7 to be guided to a liquidcrystal display device 101 for red color display, a second dichroicmirror 9 for allowing only a green color component G in the transmittedbeam which is transmitted through the first dichroic mirror 7 to bereflected and guiding it to a liquid crystal display device 501 forgreen color display and for allowing the blue color component B to betransmitted and guiding it to a liquid crystal display device 601, athird dichroic mirror 13 for allowing a video image which is transmittedthrough the liquid crystal display device 501 to be combined with avideo image transmitted through the liquid display device 101, a secondreflection mirror 15 for allowing a video image which is transmittedthrough the liquid crystal display 601 to be combined with a video imagetransmitted through the liquid crystal display device 101 and a fourthdichroic mirror 17. The video image thus combined is condensed by acondensing lens 19 and, after passing through an aperture in a secondaperture mask 21, projected on a projection lens 31.

FIG. 2 is a view schematically showing an arrangement of the liquidcrystal display device 101 in FIG. 1. The other liquid crystal displaydevices 501 and 601 are substantially the same as the liquid crystaldisplay device 101 and any further explanation is, therefore, omitted.

The liquid crystal display device 101 has one pair of electrodesubstrates 111 and 191 and a high polymer molecule dispersed-typenematic liquid crystal cell 103 held between the substrates 111 and 191.The liquid crystal cell 103 comprises a high polymer molecular resinmaterial and an anisotropic nematic liquid crystal having a positivepermittivity dispersed in the high polymer molecular resin material.

One electrode substrate 111 includes, over a quartz transparentinsulating substrate, one set of scanning line drive circuits 201a and201b arranged on the left and right sides of the liquid crystal cell 103in a redundant way, one set of video signal line drive circuits 301a and301b arranged on the upper and lower sides of the liquid crystal cell103 in a redundant way, 1035 scanning lines 161 (Yj: j=1, 2, . . . ,1035) connected to one set of scanning line drive circuits 201a and201b, respectively, and 1840 video signal lines 163 (Xi: i=1, 2, . . . ,1840) connected to another set of video signal line drive circuits 301aand 301b. Thin-film transistors (hereinafter referred to as TFTs) areelectrically connected at their gates to the scanning lines 161 and attheir drains to the video signal lines 163 and formed of polysilicon.Further, pixel electrodes 167 are electrically connected to the sourcesof the TFTs 165 and comprised of ITO (Indium-Tin-Oxide) and subsidiarycapacitive lines 169 are integrally arranged substantially parallel tothe scanning lines 161 to each form a subsidiary capacitance CSelectrically connected in parallel to the pixel electrode 167.

The other electrode 191 are so arranged as to provide a common electrode195 over the transparent insulating substrate, the common electrodebeing formed of ITO.

In the liquid crystal display devices 101, 501 and 601, 1840 displaypixels are each comprised of a high polymer molecule dispersed-typenematic liquid crystal cell 103 held between the pixel electrode 167 andthe common electrode 195 and 1035 horizontal pixel lines are provided,the same thing can also be said of a display image which, whentransmitted, is projected on the respective liquid crystal displaydevices 101, 501 and 601.

One scanning line drive circuit 201a will be explained below withreference to FIG. 3. In this embodiment, since the scanning line drivecircuit 201a is substantially the same in structure as the otherscanning line drive circuit 201b, any further explanation of the drivecircuit 201b is omitted.

The scanning line drive circuit 201a comprises a numeral signalconverting circuit section 211a, a scanning select circuit section 221aconnected to the numeral signal converting circuit section 211a, bufferamplifiers 231a connected to the scanning select circuit section 221a,and an output control circuit section 241a connected to the bufferamplifiers 231a.

The numeral signal converting circuit section 211a comprises 20 numeralsignal lines 212a having 10 non-inverted signal lines for supplying a10-bit digital numeral signal SA1-SA10 and 10 inverted signal lines forsupplying a digital numeral signal SA11-SA20, which is an invertedreplica of the digital numeral signal SA1-SA10 , stages of logic circuitsections 215a each including a set of three-input NOR gates NO1-NO4, andstages of matrix connection section 213a each connecting those selectedfrom the non-inverted and inverted signal lines in each common bit tothe three-input NOR gates NO1 to NO4 in the logic circuit section 215aof a corresponding stage.

The 10-bit non-inverted and inverted signal lines are selected as adifferent combination for each matrix connection section 213a. In afirst stage matrix connection section 213a for example, selection ismade of a 10th-bit (2⁹) non-inverted signal line, a 9th-bit (2⁸)non-inverted signal line, a 8th-bit (2⁷) non-inverted signal line, a7th-bit (2⁶) non-inverted signal line, a 6th-bit (2⁵) non-invertedsignal line, a 5th-bit (2⁴) non-inverted signal line, a 4th-bit (2³)non-inverted signal line, a 3rd-bit (2²) non-inverted signal line, a2nd-bit (2¹) non-inverted signal line and a 1st-bit (2⁰) inverted signalline. In the second stage matrix connection section 213a, selection ismade of a 10th-bit (2⁹) non-inverted signal line, a 9th-bit (2⁸)non-inverted signal line, a 8th-bit (2⁷) non-inverted signal line, a7th-bit (2⁶) non-inverted signal line, a 6th-bit (2⁵) non-invertedsignal line, a 5th-bit (2⁴) non-inverted signal line, a 4th-bit (2³)non-inverted signal line, a 3rd-bit (2²) non-inverted signal line, a2nd-bit (2¹) inverted signal line and a 1st-bit (2⁰) non-inverted signalline.

The logic circuit sections 215a have, for example, 518 stages, thenumber of which is smaller than that of 1035 scanning lines 161 (Yj:j=1, 2, . . . , 1035). The logic circuit section of each stage includesfour 3-input NOR gates NO1 to NO4, two 2-input NAND gates NA1 and NA2and one 2-input NOR gates NO5. The outputs of the NOR gates NO1 and NO2are connected to first and second input terminals of NAND gates NA1. Theoutputs of the NOR gates NO3 and NO4 are connected to first and secondinput terminals of NAND gates NA2. The output terminals of the NANDgates NA1 and NA2 are connected to first and second input terminals ofthe NOR gate NO5.

The output signal of the NOR gate NO5 of each logic circuit section 215ais supplied to the scanning select circuit 221a. In the scanning selectcircuit section 221a, the output signal of the NOR gate NO5 of eachlogic circuit section 215a is divided into three parts and supplied tofirst input terminals of the first, second and third 2-input NAND gatesNA3 to NA5. Second input terminals of these NAND gates NA3 to NA5 areconnected to three scanning lines A, B and C. The output terminal of thefirst NAND gate NA3 is connected to a second input terminal of a 2-inputNOR gate NO6, which is also provided for a NAND gate NA5 of thepreceding stage logic circuit section 215a. The output terminal of thesecond NAND gate NA4 is connected to a first input terminal of a 2-inputNOR gate NO7. A second input terminal of the NOR gate 7 is connected toa power supply terminal set at an ON level. The output terminal of thethird NAND gate NA5 is connected to a first input terminal of another2-input NOR gate NO6, which is provided also for a NAND gate NA3 of thesubsequent stage logic circuit section 215a.

The output signals of NOR gates NO6 and NO7 are fed through the bufferamplifiers 231a to the output control circuit section 241a. The outputcontrol circuit section 241a is controlled by output control signals VG0and VG1 fed respectively through output control lines G0 and G1. Theoutput control signal VG1 is an inverted replica of the output controlsignal VG0, and the output control circuit section 241a determines onthe basis of the output signals VG0 and VG1 whether or not the bufferamplifier 231a is to be connected to a corresponding scanning line 161.

In a case where a defective operation occurs, for example, in theone-side scanning line drive circuit 201a, the scanning line drivecircuit 201a is electrically disconnected from the scanning line 161, sothat the other-side scanning line drive circuit 201b can operate withoutbeing adversely affected by the one-side scanning line drive circuit201a.

With reference to FIG. 4, explanation will be given below about a casewhere the scanning line driving circuit 201a is used for atwo-line-at-a-time drive operation for selecting the scanning lines twoby two to appropriately display the video signal VS over TVbroadcasting, etc., and simultaneously driving the two scanning lines ofeach selection, wherein the selection is made such that the combinationof two scanning lines is different between an odd-number field periodand even-number field period.

The numeral signal lines 212a receives a 10-bit digital numeral signalSA1-SA10 from a count circuit or the like and a 10-bit digital numeralsignal SA10-SA20 from the count circuit or the like via an invertingoutput circuit. The digital numeral signal SA1-SA10 is sequentiallyadded as {0000000001}, {0000000010} {0000000011}, . . . for every twohorizontal scanning period as shown in FIG. 4(a), and the respectivebits thereof are supplied to a 2⁹ signal line, 2⁸ signal line, 2⁷ signalline, 2⁶ signal line, 2⁵ signal line, 2⁴ signal line, 2³ signal line, 2²signal line, 2¹ signal line and 2⁰ signal line of the numeral signallines 212a. The inverted digital numeral signal SA11-SA20 issequentially subtracted as {1111111110}, {1111111101}, {1111111100} . .. (not shown), and the respective bits thereof are supplied to a 2⁹inverted signal line, 2⁸ inverted signal line, 2⁷ inverted signal line,2⁶ inverted signal line, 2⁵ inverted signal line, 2⁴ inverted signalline, 2³ inverted signal line, 2² inverted signal line, 2¹ invertedsignal line and 2⁰ inverted signal line of the numeral signal lines212a. For example, when the digital numeral signal SA1-SA10 from thecount circuit emerge as a {0000000001} shown in FIG. 4(a), a {0} issupplied to the 2⁹ signal line, 2⁸ signal line, 2⁷ signal line, 2⁶signal line, 2⁵ signal line, 2⁴ signal line, 2³ signal line, 2² signalline, 2¹ signal line and 2⁰ inverted signal line, and a {1} is suppliedto the 2⁹ inverted signal line, 2⁸ inverted signal line, 2⁷ invertedsignal line, 2⁶ inverted signal line, 2⁵ inverted signal line, 2⁴inverted signal line, 2³ inverted signal line, 2² inverted signal line,2¹ inverted signal line and 2⁰ signal line.

When a {0000000001} is input as the digital numeral signal SA1-SA10 ,only an output S1 is obtained from the first stage of the numeral signalconverting circuit section 211a, as shown in FIG. 4(b). Similarly, whenthe digital numeral signal SA1-SA10 is output as a {0000000010} from thecount circuit, then a {0} is supplied to the 2⁹ signal line, 2⁸ signalline, 2⁷ signal line, 2⁶ signal line, 2⁵ signal line, 2⁴ signal line, 2³signal line, 2² signal line, 2⁰ signal line and 2¹ inverted signal lineof the numeral signal line 212a and a {1} is supplied to the 2⁹ invertedsignal line, 2⁸ inverted signal line, 2⁷ inverted signal line, 2⁶inverted signal line, 2⁵ inverted signal line, 24 inverted signal line,2³ inverted signal line, 2² inverted signal line, 2⁰ inverted signalline and 2¹ signal line. In consequence, only an output S2 is obtainedfrom the second stage of the numeral signal converting circuit section211a upon the inputting of the digital numeral signal {0000000010}.

As shown in FIG. 4(c), a select signal VA is applied to the firstscanning select line A, noting that it is placed in an ON level duringthe first field period and in an OFF level during the second fieldperiod; a select signal VB which is placed at a given ON level isapplied to the second scanning select line B; and an inverted replica VCof the select signal VA is applied to the third scanning select line C.

Using the output S of the numeral signal converting circuit section andrespective select signals VA, VB and VC of the respective scanningselect lines A, B and C, a scanning signal VYj is output to two adjacentscanning lines 161 for each horizontal scanning period, as shown in FIG.4(d). The combination of two scanning lines 161 selected at a time ismade different between the first and second field periods.

With reference to FIG. 5, explanation will be given below about a casewhere the scanning drive circuit 201a is used for an interlace driveoperation of selectively scanning the odd-number scanning lines duringthe odd-number field period and the even-number scanning lines duringthe even-number field period in an alternate way to appropriatelydisplay the video signal VS on television broadcast, etc.

When the 10-bit digital numeral signal SA1-SA10 and 10-bit inverteddigital numeral signal SA11-SA20 are input to the numeral signal lines212a as in the same way as set out above, outputs S as shown in FIG.5(b) is obtained from the respective stages of the numeral signalconverting circuit section 211a.

As shown in FIG. 5(c), a select signal VA, which is placed in the ONlevel during the first field period and in the OFF level during thesecond field period, is supplied to the first scanning select line A, aninverted replica VB of the select signal VA is supplied to the secondscanning select line B and a select signal VC of a given OFF level issupplied to the third scanning select line C.

Scanning signals VYj are output from the scanning lines 161, on everyother for each horizontal scanning period, according to the output ofthe numeral signal converting circuit section 211a and select signalsVA, VB and VC on the scanning select lines A, B and C as shown in FIG.5(d). A different select scanning 161 is made on the first field periodand on the second field period.

With reference to FIG. 6, explanation will be given below about the casewhere the scanning line drive circuit 211a is used for a sequentialdrive operation of selecting all the scanning lines during each verticalscanning period to appropriately display the video signal VS, such as acomputer signal.

When, as in the same way as set out above, 10-bit digital numeral signalSA1-SA10 and 10-bit inverted digital numeral signal SA11-SA20 are inputto the numeral signal lines 212a as shown in FIG. 6(a), outputs S shownin FIG. 6(b) are obtained from the respective stages of the numeralsignal converting circuit 211a as shown in FIG. 6(b).

As shown in FIG. 6(c), a select signal VA for varying one period toone-half horizontal scanning period is applied to the first scanningselect line A, an inverted replica VB of the select signal VA issupplied to the second scanning select line B and a select signal VC fortaking a given OFF level is applied to the third scanning line C.

Scanning signals VYj which are for sequentially selectively scanning twoscanning lines during one horizontal scanning period, are output fromthe scanning lines 161 according to the output of the numeral signalconverting circuit section 211a and select signals VA, VB and VC on thescanning select lines A, B and C as shown in FIG. 6(d).

A two-lines-at-a-time drive, interlace drive and sequential scanningdrive operations can be selected in accordance with the input digitalnumeral signal SA1-SA10 and scanning select signals VA, VB and VC on thescanning select lines A, B and C in the manner explained above.

With reference to FIG. 7, the video signal line drive circuit 301a ofthe liquid crystal display device 101 will be explained below In thisembodiment, since the video signal line drive circuit 301a hassubstantially the same arrangement as the other video signal line drivecircuit 301b, any further explanation of the drive circuit 301b isomitted.

The video signal line drive circuit 301a comprises a numeral signalconverting circuit section 311a having both a matrix connection section313a and logic circuit sections 315a, buffer amplifiers 321a connectedto the numeral signal converting circuit 311a, an output control circuitsection 331a connected to the buffer amplifiers 321a, a video signalselect circuit 341a connected to the output control circuit section331a, and a storage capacitance section 351a.

The numeral signal conversion circuit section 311a comprises 18 numeralsignal lines 312a. There are nine non-inverted signal lines forsupplying a 9-bit digital numeral signal DA1-DA9 and nine invertedsignal lines for supplying an inverted replica DA10-DA18 of the digitalnumeral signal DA1-DA9, stages of logic circuit sections 315a, eachincluding a set of 3-input NAND gates NA1-NA3, and stages of matrixconnection sections 313a connecting each line selected from thenon-inverted and inverted signal lines in the respective common bits tothe 3-input NAND gates NA1-NA3 of a corresponding stage.

The 9-bit non-inverted and inverted signal lines are selected in adifferent combination for each matrix connection section 313a. In thefirst stage matrix connection section, for example, a 9th-bit (2⁸)inverted signal line, 8th-bit (2⁷) inverted signal line, 7th-bit (2⁶)inverted signal line, 6th-bit (2⁵) inverted signal line, 5th-bit (2⁴)inverted signal line, 4th-bit (2³) inverted signal line, 3rd-bit (2²)inverted signal line, 2nd-bit (2¹) inverted signal line and 1st-bit (2⁰)non-inverted signal line are selected. In the second stage matrixconnection section 313a, though being not shown, a 9th-bit (2⁸)non-inverted signal line, 8th-bit (2⁷) non-inverted signal line, 7th-bit(2⁶) non-inverted signal line, 6th-bit (2⁵) non-inverted signal line,5th-bit (2⁴) non-inverted signal line, 4th-bit (2³) non-inverted signalline, 3rd-bit (2²) non-inverted signal line, 2nd-bit (2¹) invertedsignal line, and 1st-bit (2⁰) non-inverted signal line are selected.

Each logic circuit section 315a comprises three 3-input NAND gatesNA1-NA3 and one 3-input NOR gate NO1. The output terminals of the NANDgates NA1-NA3 are connected to first, second and third input terminalsof the 3-input NOR gate NO1. The output signal of the NOR gate NO1 isfed through the buffer amplifier 321a to the output control circuitsection 331a. In the output control circuit section 331a, the outputsignal of the NOR gate NO0 of each logic circuit section 315a is dividedinto eight ones which are supplied via corresponding buffer amplifiers333a to first input terminals of eight 2-input NOR gates NO2. An outputcontrol line G2 is connected to second input terminals of the NOR gatesNO2.

The output signals of the NOR gate NO2 are supplied as output signals ofthe output control circuit section 331a to the video signal selectcircuit section 341a where they are input to the gates of eight analogswitches 343a provided for video data selection. The drains of theseanalog switches 343a are connected to eight video signal input lines345a and, when the respective outputs S of the output control circuitsection 331a are placed in an ON period, video signals VS1, . . . , VS8are sample-output from the sources of the analog switches 343a. Eachvideo data VD sampled by the video signal select circuit section 341a issupplied to the corresponding video signal line 163 via the storagecapacitance section 351a for storing the data.

The operation of the video signal line drive circuit 301a will beexplained below with reference to FIG. 8.

As shown in FIG. 8(a), the 9-bit digital numeral signal DA1-DA9 issequentially added by the count circuit or the like (not shown) in sucha timing as to selectively output video data VD to the video signal line163. In each timing, when the digital numeral signal DA1-DA9 is outputby the counter (not shown) to the 2⁸ signal line, 2⁷ signal line, 2⁶signal line, 2⁵ signal line, 2⁴ signal line, 2³ signal line, 2² signalline, 2¹ signal line and 2⁰ signal line of the numeral signal lines312a, then the inverted replica DA10-DA18 of the digital numeral signalsDA1-DA9 is output from an inverting output circuit (not shown) to the 2⁹inverted signal line, 2⁸ inverted signal line, 2⁷ inverted signal line,2⁶ inverted signal line, 2⁵ inverted signal line, 2⁴ inverted signalline, 2³ inverted signal line, 2² inverted signal line, 2¹ invertedsignal line and 2⁰ inverted signal line.

For example, when the digital numeral signal DA1-DA9 from the countercircuit emerge as {0000000001}, then a {0} is supplied to the 2⁸ signalline, 2⁷ signal line, 2⁶ signal line, 2⁵ signal line, 2⁴ signal line, 2³signal line, 2² signal line, 2¹ signal line and 2⁰ inverted signal line.Further, a {1} is supplied to the 2⁹ inverted signal line, 2⁸ invertedsignal line, 2⁷ inverted signal line, 2⁶ inverted signal line, 2⁵inverted signal line, 2⁴ inverted signal line, 2³ inverted signal line,2² inverted signal line, 2¹ inverted signal line and 2⁰ signal line. Inconsequence, when the input digital numeral signal DA1-DA9 is{0000000001}, an output S1 is obtained from the first stage of theoutput control circuit section 331a as shown in FIG. 8(b).

Further, video signals VS1, . . . , VS8 are input to the eight videodata lines 345a as shown in FIG. 8(c).

When the output S from the first stage of the output control circuitsection 331a is placed in an ON period, the first to eighth video dataselect analog switches 343a are selected at a time and the respectivevideo data VD1, . . . , VD8 are output to the first to eighth videosignal lines 163.

Further, when an output S2 from the second stage of the output controlcircuit section 331a is placed during an ON period, the correspondingvideo data select analog switches 343a are selected at a correspondingtime and the respective video data VD9, . . . , VD16 are output to theninth to sixteenth video signal lines 163.

Thus, the video data VD1, . . . , VD1840 are output to the 1840 videosignal lines 163 for each horizontal scanning period.

The video data VD delivered to the video signal line 163 is written intothe pixel electrode 167 via TFT 165 during the period in which thescanning line 161 is selected, and a potential difference between thepixel electrode 167 and the common electrode 195 is held to display itduring the period before the scanning line 161 is selected again.

The number of effective scanning lines and that of video data of thevideo signal VS can be smaller than the number of the horizontal pixellines of the liquid crystal display device 101 and that of displaypixels contained in the horizontal pixel line, respectively. Explanationwill be given about effecting a display with the number of effectivevideo data VD of the video signal VS being 1024 per effective scanningline and the number of effective scanning lines being 768 as shown inFIG. 9.

Here, explanation will be given below about effecting a display on adisplay area 700 by a sequential drive shown in FIG. 6 with non-displayareas 901 and 903 comprised of 140 and 127 lines, respectively, at thetop and bottom portions of the display area and with non-display areas905 and 907 comprised of 408 display pixels, respectively, at the leftand right sides of the display area as shown, for example, in FIG. 9.

In one vertical scanning period of a first field period, the scanningline drive circuit 201a shown in FIG. 2 selects the 141st to 908thhorizontal pixel lines based on the 10-bit digital numeral signalSA1-SA10 which is sequentially increased from {0001000111} to{0111000110} by a ROM. In a first vertical blanking period of the firstfield period, the 1st to 28th horizontal pixel lines are sequentiallyscanned, as a first block 701, based on the 10-bit digital numeralsignal SA1-SA10 which is sequentially increased from {0000000001} to{0000001110} by the ROM. In a fifth vertical blanking period of thesubsequent fifth field period, the 113rd to 140th horizontal pixel linesare sequentially scanned, as a fifth block 705, based on the 10-bitdigital numeral signal SA1-SA10 which is sequentially increased from{0000111001} to {0001000110} by the ROM. In a sixth vertical blankingperiod of the sixth field period, the 909th to 936th horizontal pixellines are sequentially scanned, as a sixth block 706, based on the10-bit digital numeral signal SA1-SA10 which is sequentially increasedfrom {0111000111} to {0111010100} by the ROM. In a 10-th verticalblanking period of the subsequent 10-th field period, the 1021st to1035th horizontal pixel lines are sequentially scanned, as a 10-th block710, based on the 10-bit digital numeral signal SA1-SA10 which issequentially increased from {0111111111} to {1000000110} by the ROM.

To the video input lines 345a of the video signal line drive circuit301a, 1024 video data VD corresponding to the 409th to 1432th displaypixels during one horizontal scanning period and a video signalcontaining non-display data VB corresponding to the 1st to 408thnon-display pixels and non-display data VB corresponding to the 1433rdto 1840th non-display pixels during its horizontal blanking period areinput.

During the vertical blanking period of each field period, non-displaydata VB corresponding to the 1840 display pixels are input to the videoinput lines 345a.

By doing so, the 136th to 903th horizontal pixel lines are sequentiallyselected during one vertical scanning period and the non-display data VBare displayed, as a first block 701, on the 1st to 28th horizontal pixellines during its vertical blanking period. This being sequentiallyrepeated, the non-display data VB are displayed on all the non-displayareas 901 and 903 divided in 10 blocks.

It is sometimes difficult to transfer the non-display data VBcorresponding to the 1st to 408th non-display pixels and non-displaydata VB corresponding to the 1433th to 1840th non-display pixels withinthe horizontal blanking period. In such a case, all the non-display dataVB corresponding to the 1st to 408th non-display pixels and non-displaydata VB corresponding to the 1433rd to 1840th non-display pixels are notdisplayed during the same one horizontal scanning period but may bedisplayed in a way divided in a plurality of blocks.

The non-display areas 901 to 904 may be obtained by transferring thenon-display data VB corresponding to the 1st to 80th non-display pixelsfor each horizontal blanking period during one vertical scanning periodof the first field period, the non-display data VB corresponding to the81st to 160th non-display pixels for each horizontal blanking periodduring one vertical scanning period of the second field period, and thenon-display data VB corresponding to the 1752nd to 1840th non-displaypixels for each horizontal blanking period during one vertical scanningperiod of the subsequent eleventh field period, for example.

Further, for each field period, the non-display pixels corresponding tothe non-display data need not be made equal in respective horizontalpixel lines, and instead may be respectively made different. Therefore,it is possible to divide the non-display area into a plurality of blocksand display the non-display data on different non-display pixels foreach horizontal pixel line. For example, during the first field period,the non-display data VB are displayed on the 1st to 80th non-displaypixels with respect to the 141st to 142rd horizontal pixel lines, on the81th to 146th non-display pixels with respect to the 143th and 144thhorizontal pixel lines, and on the 161st to 240th non-display pixelswith respect to the 145th to 142nd horizontal pixel lines. As for the143th to 144th horizontal pixel lines, since the non-display data VBcorresponding to the 1st to 80th non-display pixels are held in thehorizontal capacitance sections 351a at the time of displaying the 141thand 142th horizontal pixel lines and remain there, the non-display dataVB corresponding to the 1st to 80th non-display pixels need not betransferred. Accordingly, while the non-display data VB are displayed onthe 1st to 80th non-display pixels, the non-display data VB aredisplayed on the 81th to 160th non-display pixels.

With the liquid crystal display device 101 arranged as described above,the display area 700 can easily be located at substantially the centralarea of the display screen by controlling the digital numeral signalinput to the scanning line drive circuits 201a and 201b and video signaldrive circuits 301a and 301b.

Regarding the video signal drive circuits 301a and 301b, it effectivelyutilizes the memory function of the storage capacitance section 351a, sothat the non-display area can be obtained without using any specificframe memory or the like, even if a lot of non-display pixels are set ineach horizontal pixel line.

The digital numeral signal SA1 to SA20 may be determined to select the136th to 903th horizontal pixel lines during one vertical scanningperiod, and to sequentially select the 1st, 11st, 21st, . . . ,horizontal pixel lines as a first block during a first vertical blankingperiod, the 2nd, 12nd, 22nd, . . . , horizontal pixel lines as a secondblock during the second vertical blanking line period, the 3rd, 13rd,23rd, . . . , horizontal pixel lines as a third block during the thirdvertical blanking period, and the 10th, 20th, 30th, . . . , horizontalpixel lines as a 10th block during . . . 10th vertical blanking period.

Since the non-display areas 901 and 903 are dividedly driven, thehorizontal pixel lines constructing the non-display areas 901 and 903selected during one vertical blanking period are uniformly dispersed ina display screen as compared with the above-mentioned procedure.Therefore, even if the number of blocks dividing the non-display areas901 and 903 is increased, it is possible to attain a better displayimage without involving a flicker, etc.

Although, in this embodiment, the non-display areas 901 and 903 aredivided into 10 blocks in the vertical scanning direction and thenon-display data (VB) are written onto every horizontal pixel line ofthe non-display areas 901 and 903 during the 10-times vertical blankingperiod, needless to say, all the horizontal pixel lines constituting thenon-display areas 901 and 903 are selected at a particular time.

The same thing can also be said about the case where the non-displaydata (VB) is written in one horizontal pixel line.

In the case where, as set out above, the number of effective scanninglines for the video signals VS and that of the video data VD are smallerthan the number of the horizontal pixel lines of the liquid crystaldevice 101 or the number of display pixels constituting one horizontalpixel line, it follows that, according to the liquid crystal projector 1shown in FIG. 1, the display area 700 and non-display areas 901, 903,905 and 907 are displayed on the screen 41 as shown, for example, inFIG. 9.

In such a case, the liquid crystal projector 1 may be arranged such thata decrease in the number of effective scanning lines of the video signalVS or the number of effective video data VD is detected, and themagnification of the projecting lens 31 thereof is increased based onthe result of detection. Thus, even when the number of effectivescanning lines of the video signal VS or the number of effective videodata VD varies, it is possible to obtain a display area 700 of asubstantially constant size on the screen 41 at all times.

As described above, according to the liquid crystal device 101 of thepresent invention, the respective scanning lines 161 and analog switches343a for respective video data selection are selected responsive to theinput digital numeral signals SA1-SA20 and DA1-DA18. Thus, according tothe liquid crystal display device 101 of this embodiment, the scanninglines 161 and video data select analog switches 343a are sequentiallyselected as set out above and, in addition, it is also possible toselect any scanning lines 161 and video data select analog switches 343aby the digital numeral signals SA1-SA20 and DA1-DA18 applied to thenumeral signal lines 212a and 312a.

According to the liquid crystal projector 1 of this embodiment, even ifthe number of horizontal pixel lines differs from that of the effectivescanning lines of the video signal VS or even if the number of thedisplay pixels constituting one horizontal pixel line differs from thatof the video data VD constituting one effective scanning line, it ispossible to obtain a display area and non-display areas at any locationon the display screen.

According to the liquid crystal projector 1 of this invention, even ifthe number of horizontal pixel lines greatly differs from that ofeffective scanning lines of the video signal VS or even if the number ofdisplay images constituting one horizontal pixel line greatly differsfrom that of video data VD constituting one effective scanning lines, itis possible to obtain a display area and non-display areas at anylocation on the display screen by dividedly scanning the horizontalpixel lines of the non-display area during plural vertical blankingperiods or dividedly applying the non-display data VB to the displaypixels of the non-display area during plural horizontal blanking periodsof the vertical scanning period.

Although, in this embodiment, the display area is located atsubstantially the central area of the display screen as set out above,the present invention is not restricted thereto. The display area can belocated in any position by controlling the digital numeral signalsSA1-SA10 and DA1-DA9. It is also possible to prepare for a multi-imagescreen.

Further, the respective scanning lines 161 and video data select analogswitches 343a can be selected in any sequence by controlling theincrement and decrement of the digital numeral signals SA1-SA10 andDA1-DA9. As already set out, the liquid crystal projector 1 of thisembodiment is comprised of, for example, three substantially similarliquid crystal display devices 101, 501 and 601. As evident from FIG. 1,however, the number of inversions of an image transmitted through theliquid crystal display device 501 only becomes odd-numbered, and it isnecessary that different handling be effected in that device in view ofthe select sequence of the video data select analog switches 343a or theselect sequence of the scanning lines 161 in the other liquid crystaldisplay devices 101 and 601. According to this embodiment, however, itis possible to use three common liquid crystal display devices 101, 501and 601 simply by connecting only the digital numeral signal, which isinput to the liquid crystal display device 501, to the counter circuitfor outputting the sequentially subtracting digital numeral signal. Itis better, in this case, to make the display pixel configurations of therespective liquid crystal devices 101, 501 and 601, substantially equalto its configuration even if the transmitted light is inverted.

According to the present invention, it is possible to mirror-invert thedisplay image and, by setting the digital numeral signals SA1-SA10 andDA1-DA9 from the counter or ROM, etc., to readily effect switchingbetween when the display image from the liquid crystal projector 1 isdisplayed on a transmission type screen and when the image is displacedon a reflection type screen.

Although, in this embodiment, the input numeral signals SA1-SA20 foroperating the scanning line drive circuit 201a constitute a 10-bitconfiguration and the input numeral signals DA1-DA18 for operating thevideo signal line drive circuit 301a constitute a 9-bit configuration,the scanning line drive circuit 201a, for example, is such that themaximal controllable number of scanning lines 161 becomes 1024 by acombination of connections at the matrix connection section 213a in thescanning line drive circuit 201a, for example.

In this embodiment, however, the scanning select circuit section 221a isprovided between the matrix connection section 213a and the scanninglines 161, whereby it is possible to effect various types of drives andto control 1035 scanning lines 161 without involving an undue increasein the bit number of the input numeral signals (SA1-SA20).

However, a corresponding measure may be taken by increasing the numberof bits of the input numeral signal or, conversely, in the case wherethe number of video signal lines 163 or number of scanning lines 161 issmall, it is possible to decrease the number of bits of the inputnumeral signals.

Although, in the above-mentioned embodiment, a cumbersome connectionoperation is eliminated by forming the scanning line drive circuits201a, 201b and video signal line drive circuits 301a, 301b integrallyover the substrate 113 as shown in FIG. 2, it may be possible toconstruct them as an external circuit using a discrete IC, etc.

It may be possible that either one of the scanning line drive circuits201a, 201b and video signal line drive circuits 301a, 301b or one ofsets of drive circuits 201a, 201b and 301a, 301b is constructed of aplurality of stages of shift registers as in the conventional structureor a different connection configuration is adopted between the numeralsignal lines 212a and the logic circuit section 215a at the matrixconnection section 213a with the scanning line drive circuits 201a, 201bon both sides.

Although, in the embodiment, explanation has been given about the casewhere the high polymer diffused type liquid crystal is employed, whichcan largely enhance the light utilization efficiency because ofeliminating any polarizing plate, etc., the present invention is notrestricted thereto and use can be made of conventionally known types ofliquid crystal materials.

Between the pixel electrode and the common electrode, for example, anematic liquid crystal with a positive dielectric anisotropy (not shown)may be held, as the respective liquid crystal display devices 101, 501and 601, to allow liquid crystal molecules to be twisted 90° twistedthrough opposed alignment films on these electrodes so that a polarizingplate is arranged on the outer surface of the substrate to align thepolarization axis with the alignment axis.

Thus, the so-called normally white mode liquid crystal devices 101, 501,601 are constructed in which, as shown in FIG. 10, when a potentialdifference between the pixel electrode and the common electrode is at a0 V the transmittance becomes maximal and decreases with an increasingpotential difference.

According to the liquid crystal projector 1 using the thus constructednormally white mode liquid crystal display deices 101, 501 and 601, whenthe non-display data VB are written into the non-display areas 901, 903and 905, 907 shown in FIG. 9, a drive voltage is selected in a potentialdifference region 63 other than the potential difference region 61across the pixel electrode, and the common electrode which may be takenin a normal display state and, by doing so, the non-display areas 901,903 and 905, 907 are divided as a plurality of blocks. Thus, if displayis completed in a plurality of blocks, it is possible to secure a betterblack display.

Although in this embodiment the liquid crystal projector 1 comprised ofthe three liquid crystal display devices 101, 501 and 601 has beenexplained by way of example, needless to say, it may be constructed ofone crystal display device. Further, the optical system used may be madefrom various types of systems and the liquid crystal display device maybe of a direct-viewing type.

Although in this embodiment the liquid crystal pixels have beenexplained as the display element, the present invention can beeffectively applied if use is made of a display device having an elementcapable of light modulation, such as a display element whose lighttransmittance or reflectance varies in accordance with a drive voltageand a display element whose light emitting amount varies by a drivevoltage.

Further, according to this embodiment, the respective numeral signalconverting circuit sections may be altered to allow predeterminednothing-producing digital numeral signals, such as all 0 bits, to beinserted between any digital numeral signal trains. Since thepredetermined digital numeral signals prevent the duplication of outputpulses, it is possible to stably operate the display device.

Industrial Applicability

According to the display device of the present invention, since fewerlogic circuit sections are provided than the number of scanning lines orsignal lines for selective outputting by the scanning circuit section orvideo signal supply circuit section on the basis of the input numeralsignals from the select control circuit section, it is possible to, forthe high definition of the display device, prevent an increase in thenumber of connections and of logic circuit sections transmitting numeralsignals and hence to manufacture devices in a high yield.

Further, according to the drive method for the display device of thepresent invention, even if the number of horizontal pixel lines of thedisplay panel and effective scanning lines of the video signals, or thenumber of display pixels constituting one horizontal pixel line andnumber of video data of video signals, differ, it is possible to displaynon-display data on non-display areas by, for example, displayingnon-display data in a first period on at least one horizontal pixel linenot corresponding to the effective scanning lines of the video signalswhile, at the same time, displaying non-display data, in a second perioddifferent from the first period, on a horizontal pixel line notcorresponding to the effective scanning line of the video signals or bydisplaying non-display data, in a first period, on at least one displaypixel not corresponding to video data while, at the same time,displaying non-display data, in a second period different from the firstperiod, on other display pixels not corresponding to the video data. By,providing a logic circuit section for effecting the selective outputtingof the scanning circuit section or video signal supply circuit sectionon the display device, it is possible to readily realize theabove-mentioned drive method in a simpler circuit arrangement.

We claim:
 1. A display device comprising:a display panel having adisplay screen constructed by a plurality of signal lines and aplurality of scanning lines arranged in a matrix, switching elementselectrically connected to said signal lines and scanning lines and pixelelectrodes connected to said switching elements; a select controlcircuit section for generating an n-bit input numeral signal, n being apositive integer equal to or greater than 2, and an inverted replica ofthe input numeral signal and for controlling the n-bit input numeralsignal so as to locate a display area at a position variable within thedisplay screen; and a video signal supplying circuit section forselecting, in predetermined timings, input video signals based on theinput numeral signal and the inverted replica of the input numeralsignal from said select control circuit section, and supplying selectedvideo signals to said signal lines as video data, wherein said videosignal supplying circuit section includes:an input connection line grouphaving sets of input connection lines for receiving bits of the inputnumeral signal and bits of the inverted replica of the input numeralsignal, a plurality of logic circuit sections, fewer in number than saidscanning lines, for responding to combinations of the input numeralsignal and the inverted replica of the input numeral signal, and outputdistributing means for assigning an output from one logic circuitsection to at least two signal lines.
 2. The display device according toclaim 1, wherein each logic circuit section comprises a first logiccircuit connected to different input connection lines of one set, asecond logic circuit connected to different input connection lines ofanother set and a third logic circuit for responding to outputs of saidfirst and second logic circuits.
 3. The display device according toclaim 1, wherein said video signal supplying circuit section comprises aplurality of video signal input lines for receiving the video signalsand analog switching means for obtaining a plurality of video data fromsaid video signal input lines on the basis of an output of one logiccircuit section.
 4. The display device according to claim 1, whereinsaid switching elements and video signal supplying circuit section areintegrated on one substrate for said display panel.
 5. A method fordriving a display device for displaying a display image based on videodata of a video signal on a display panel including a display screenconstructed by an array of horizontal pixel lines each having aplurality of display pixels, the method comprising:supplying an n-bitinput numeral signal and an inverted replica of said input numeralsignal; displaying non-display data in a first period on at least onehorizontal pixel line not corresponding to an effective scanning line ofthe video signal when the number of effective scanning lines in onevertical scanning period of the video signal is less than the number ofsaid horizontal pixel lines, said display of the non-display data in thefirst period being based on said input numeral signal; and displayingnon-display data in a second period different from the first period onanother horizontal pixel line not corresponding to the effectivescanning line of the video signal, thereby locating a display area onany position of the screen.
 6. The method according to claim 5, whereinthe first and second periods are a vertical blanking period of the videosignal.
 7. The method according to claim 5, wherein said display panelis a liquid crystal panel formed of an array substrate having a pixelelectrode arranged in a matrix array, a counter substrate having acounter electrode arranged opposite to said pixel electrode, and aliquid crystal cell held between said array substrate and said countersubstrate.
 8. The method according to claim 7, wherein a potentialdifference for displaying non-display data is determined to be outside arange of a potential difference set between said pixel electrode andsaid counter electrode to display video data.
 9. The method according toclaim 5 which comprises a scanning circuit section including a scanningcontrol circuit section for supplying the n-bit input numeral signal (n:2 or more positive integer) and the inverted replica of the inputnumeral signal, an input connection line group having sets of inputconnection lines for receiving bits of the input numeral signal and bitsof the inverted replica of the input numeral signal so as to select atleast one horizontal pixel line corresponding to the input numeralsignal and the inverted replica of the input numeral signal, and logiccircuit sections for responding to combinations of the input numeralsignal and the inverted replica of the input numeral signal.
 10. Amethod for driving a display device for displaying a display image basedon video data of a video signal on a display panel including a displayscreen constructed by an array of horizontal pixel lines each having aplurality of display pixels, the method comprising the stepsof:supplying an n-bit input numeral signal and an inverted replica ofsaid input numeral signal; displaying non-display data, in a firstperiod, on at least one display panel not corresponding to the videodata, said display of said non-display data in the first period beingbased on said input numeral signal; and displaying non-display data in asecond period different from the first period, on another display pixelnot corresponding to the video data, wherein the non-display data isdisplayed in the first and second periods when the number of the videodata in one horizontal scanning period of the video signal is less thanthe number of said display pixels of the horizontal pixel line, therebylocating a display area on any position of the display screen.
 11. Themethod according to claim 10, wherein the first and second periods areone horizontal blanking period of the video signal.
 12. The methodaccording to claim 10, wherein said display panel is a liquid crystalpanel formed of an array substrate having said pixel electrodes arrangedin a matrix array, a counter substrate arranged opposite to said pixelelectrode, and a liquid crystal cell held between said array substrateand said counter substrate.
 13. The method according to claim 12,wherein, a potential difference for displaying non-display data isdetermined to be outside a range of a potential difference set betweensaid pixel electrode and said counter electrode to display video data.14. A display device comprising:a display panel having a display screenconstructed by a plurality of signal lines and a plurality of scanninglines arranged in a matrix array, a plurality of switching elementselectrically connected to said signal lines and scanning lines, pixelelectrodes connected to said switching elements, and an array ofhorizontal pixel lines each comprised of a plurality of display pixels;a scanning control circuit section for controlling an n-bit inputnumeral signal, n being a positive integer equal to or greater than 2,to locate a display area at a position variable within the display, andfor supplying an n-bit input numeral signal and an inverted replica ofthe input numeral signal; a scanning circuit section comprising an inputconnection line group having sets of input connection lines forreceiving bits of the input numeral signal and bits of the invertedreplica of the input numeral signal to select at least one scanning linecorresponding to the input numeral signal and the inverted replica ofthe input numeral signal and logic circuit sections for responding tocombinations of the input numeral signal, wherein said scanning controlcircuit is arranged such that, when the number of effective scanninglines in one vertical scanning period of the video signal is less thanthe number of the corresponding horizontal pixel lines, the inputnumeral signal is output to display non-display data in a first periodon at least one horizontal pixel line of the video signal and displaynon-display data in a second period different from the first period onanother horizontal pixel line not corresponding to said effectivescanning line of the video signal.
 15. The display device according toclaim 14, further comprising a projection optical system for projectingon a screen a display image corresponding to the video signal.
 16. Thedisplay device according to claim 15, further comprising adjusting meansfor adjusting said projection optical system for making the displayimage on said screen substantially equal between when the number of saideffective scanning lines in one vertical scanning period of the videosignal is less than the number of the corresponding horizontal pixellines and when the number of the effective scanning lines in onevertical scanning period of the video signal is substantially equal tothe corresponding horizontal pixel lines.
 17. A display devicecomprising:a display panel having a display screen constructed by aplurality of signal lines and a plurality of scanning lines arranged ina matrix array, a plurality of switching elements electrically connectedto said signal lines and scanning lines, pixel electrodes connected tosaid switching elements; a scanning circuit section for supplyingscanning signals to said scanning lines; and a scanning control circuitsection for controlling an n-bit input numeral signal, n being apositive integer equal to or greater than 2, to locate a display area ata position variable within the display screen, and for supplying then-bit input numeral signal and an inverted replica of the input numeralsignal to said scanning circuit section, said scanning circuit sectionhaving:an input connection line group having sets of input connectionlines for receiving bits of the input numeral signal and bits of theinverted replica signal, and a plurality of logic circuit sections,fewer in number than said scanning lines, for responding to combinationsof the input numeral signal and the inverted replica of the inputnumeral signal.
 18. A display device comprising:a display panel having adisplay screen constructed by a plurality of signal lines and aplurality of scanning lines arranged in a matrix, switching elementselectrically connected to said signal lines and scanning lines and pixelelectrodes connected to said switching elements; a select controlcircuit section for generating an n-bit input numeral signal, n being apositive integer equal to or greater than 2, and an inverted replica ofthe input numeral signal and for controlling the n-bit input numeralsignal to locate a display area at a position variable within thedisplay screen; and a video signal supplying circuit section forselecting, in predetermined timings, input video signals based on theinput numeral signal and the inverted replica of the input numeralsignal from said select control circuit section, and supplying selectedvideo signals to said signal lines as video data, wherein said videosignal supplying circuit section includes:an input connection line grouphaving sets of input connection lines for receiving bits of the inputnumeral signal and bits of the inverted replica of the input numeralsignal, and a plurality of logic circuit sections, fewer in number thansaid scanning lines, for responding to combinations of the input numeralsignal and the inverted replica of the input numeral signal.